Senior IC Verification and Validation Engineer
To support the development of our next-generation SoCs in Positioning and Cellular and Short-Range applications, we are looking for talented, innovative, self-driven and motivated senior engineer with proven concrete industrial experiences in the verification and validation of SoCs for wireless communication systems.
The key responsibilities of the successful candidate will be to own and contribute in IPs and Top level verification and validations activities in UVM, Formal Verification and FW driven methodologies while using EDA tools and in Lab environments using FPGA and ICs.
You will be working in a growing international and multi-site team responsible for SoC verification and validation.
Your Responsibilities :
Responsible for the quality of IPs and / or SoC firmware driven and UVM verification and validation of wireless communication systems
Responsible for verification and validation requirements and plans, and execution of these owned or other defined plans
Development of C based FW tests, test sequences and verification environments, verification components and functional coverage using UVM methodologies to meet verification targets
Verification of IPs and subsystems by means of Formal Verification methods and techniques : System Verilog Assertions and tools
Develop and reuse existing FW in pre- and post-silicon environments such as FPGA prototypes, ASIC simulators and lab environments
Investigate issues, debug designs, FW tests and verification benches (RTL and Gate Level) using simulation tools and board (Silicon and FPGA)
Verification and validation flow implementation and updates targeting EDA tools.
If possible, mentor and support junior team members
Your Skills and Experience :
Degree in Electrical or Communication Engineering with evidence of industrial experience (5 to 7 years) in IP / ASIC design projects
Firm expertise in Verification methodologies, their applications to concrete projects (FW driven, UVM, Functional Coverage) and hands-on expertise to develop testbenches, verification environments, verification components, Functional Coverage at block and Top level
Firm expertise with HDL languages for verification (Verilog, VHDL, SystemVerilog)
Good expertise in embedded FW development and associated flow for ARM based SoC (subsystems / top-level) used in verification, validation for wireless communication systems (LTE, GPS / GNSS or similar technologies)
Formal verification experience (SVAs in particular) is a big advantage
Knowledge and experience in other areas are also big advantage : SystemVerilog Real Number Modeling, DPIs, Python, Emulation
Prior experience in technical mentoring and supporting junior team members.
Team player, self-motivated and autonomous
Good verbal and written communications skills in English
Bonus Point :
Greek / EU citizen or holder of a Greek work permit
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