Job Description Looking for Clever Heads!
Digital IC Design Engineer
To support the design of next-generation SoCs in positioning and cellular, u-blox Athens is looking for a passionate and talented engineer, interested in digital IC design.
To work in u-blox IC team you need to be creative, innovative, enthusiastic about new technologies, and striving for excellence.
The ideal candidate will start working on real project tasks in close collaboration with other teams. Through teamwork, training and dedication to personal development, u-blox goal is that every engineer quickly learns about different aspects of designing complex SoCs, starts contributing to various project tasks, and finally develops into an expert in the field.
Key responsibilities of a digital IC engineer will be to contribute to the requirements and specification analysis phase, the micro-architectural definition, the digital design (RTL), the (static / formal) verification, synthesis, static timing analysis, gate-level simulations, power estimations and optimization of IPs.
The engineer should work with the rest of the design and verification teams to meet the targeted specifications. Finally, (s)he should be responsible to plan, track and report activities related to the implementation of the IPs.
Responsibilities
Involved in the entire design process of key IPs, including RTL design, top-level integration, verification, synthesis, timing-closure, Lint / CDC violations checking, etc.
Contribute to the requirements / specification analysis and micro-architectural definition
Perform test planning, verification coverage analysis and performance evaluation
Full IP / subsystems verification using testbench based testing and coverage-driven verification techniques
Contribute to the IP top-level integration and FPGA prototyping for early IP testing at top-level, using SW
IP API development for testing purposes (SoC-level simulation, FPGA, silicon testing)
Perform power analysis and propose design optimizations (area, timing, power)
Plan, track, and report for the key IP activities
Responsible for technical documentation and reports (English language)
Patent creation
Qualifications
PhD / MS or BS in Electrical, Electronic, Computing Engineering or equivalent experience
2+ years of industrial (or academic) experience in digital IC and FPGA flow
Excellent in logic design including algorithmic-based optimization, from power, performance and area (PPA) perspective
Exposure to power management techniques for low-power architectures
Experience in design of multiple clock and power domain architectures
Exposure to static and formal verification techniques and technologies
Exposure to low-level programming for IP, top-level, testing purposes
Experience in writing SVAs for improving RTL quality
Familiar with Unix / Linux environment, shell programming, revision control systems and scripting (C-shell, Tcl, Perl, Python)
Exposure to off-chip interfaces (DDR, I2C, UART, QSPI, SDIO, Ethernet, etc)
Familiarization with lab equipment and procedures for silicon testing
Exposure to wireless communication systems and in particular : Wi-Fi, LTE, GPS / GNSS will be considered a plus
Strive for innovation and adoption of leading edge solutions
Previous experience in working with teams while capable of working independently and precisely
Good communications skills
Greek (or EU / Schengen) citizen or holder of a valid Greek work permit
Perks and Benefits
A multicultural and international company with over 50 different nationalities
Project-based activities working with colleagues across the globe
A start-up and innovation mindset while in the process of scaling-up processes and efficiencies
Hybrid work model (40% remote / 60% office) + flexible working hours
Training and career growth opportunities
Company Bonus and Stock Option Plan
Parking lot or public transportation subscription
Relocation costs supported
Social benefits according to location : Greece : Meal Allowance, Health & Life Insurance, Private Pension Plan, 50% income tax relief for all citizens (EU and non-EU) relocating to Greece 
