Senior Digital IC Design Engineer
Αθήνα, GR
πριν από 1 μέρα
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About u-blox

u-blox (SIX : UBXN) is a global provider of leading positioning and wireless communication technologies for the automotive, industrial, and consumer markets.

Our solutions let people, vehicles, and machines determine their precise position and communicate wirelessly over cellular and short range networks.

With a broad portfolio of chips, modules, and a growing ecosystem of product supporting data services, u-blox is uniquely positioned to empower its customers to develop innovative solutions for the Internet of Things, quickly and cost-effectively.

With headquarters in Thalwil, Switzerland, the company is globally present with offices in Europe, Asia, and the USA.

Job Description

Senior Digital IC Design Engineer

To support the design of next-generation SoCs in positioning, cellular and short-range applications, u-blox Athens is looking for a passionate and talented senior engineer, interested in digital IC design.

To work in u-blox IC team you need to be creative, innovative, enthusiastic about new technologies, and striving for excellence.

The ideal candidate will start working on real project tasks in close collaboration with other teams. Through teamwork, training and dedication to personal development, u-blox goal is that every engineer quickly learns about different aspects of designing complex SoCs, starts contributing to various project tasks, and finally develops into an expert in the field.

Key responsibilities of a digital IC engineer will be to contribute / drive the requirements and specification analysis phase, the micro-architectural definition, the digital design (RTL), the (static / formal) verification, synthesis, static timing analysis, gate-level simulations, power estimations and optimization of IPs.

The engineer should work with the rest of the design and verification teams to meet the targeted specifications. Finally, (s)he should be responsible to plan, track and report activities related to the implementation of the IPs.


  • Involved in the entire design process of key IPs, including RTL design, top-level integration, verification, synthesis, timing-closure, Lint / CDC violations checking, etc.
  • Contribute to the requirements / specification analysis and micro-architectural definition
  • Perform test planning, verification coverage analysis and performance evaluation
  • Full IP / subsystems verification using testbench based testing and coverage-driven verification techniques
  • Contribute to the IP top-level integration and FPGA prototyping for early IP testing at top-level, using SW
  • IP API development for testing purposes (SoC-level simulation, FPGA, silicon testing)
  • Perform power analysis and propose design optimizations (area, timing, power)
  • Utilize and evolve u-blox digital IC and FPGA flows
  • Plan, track, and report for the key IP activities
  • Responsible for technical documentation and reports (English language)
  • Patent creation
  • Qualifications

  • PhD / MS or BS in Electrical, Electronic, Computing Engineering or equivalent experience
  • 7+ years of industrial experience in digital IC and FPGA flow
  • Excellent in logic design including algorithmic-based optimization, from power, performance and area (PPA) perspective
  • Exposure to power management techniques for low-power architectures
  • Experience in design of multiple clock and power domain architectures
  • Experience in PLL components, writing SDCs and Static-Time-Analysis
  • Exposure to static and formal verification techniques and technologies
  • Experience in efficiently porting top-level RTL in FPGA and achieving timing-closure
  • Exposure to low-level programming for IP, top-level, testing purposes
  • Experience in writing SVAs for improving RTL quality
  • Proven track record of 3rd party IPs integration : Embedded CPUs, SoC interconnects, DMAs, clock-management blocks, memories
  • Familiar with Unix / Linux environment, shell programming, revision control systems and scripting (C-shell, Tcl, Perl, Python)
  • Exposure to off-chip interfaces (DDR, I2C, UART, QSPI, SDIO, Ethernet, etc)
  • Experience in cross interaction with DfT and physical design teams
  • Familiarization with lab equipment and procedures for silicon testing
  • Exposure to Channel Coding / Decoding (LDPC, Viterbi, Polar) will be considered a plus
  • Exposure to wireless communication systems and in particular : Wi-Fi, LTE, GPS / GNSS will be considered a plus
  • Exposure to ISO26262 will be considered a plus
  • Strive for innovation and adoption of leading edge solutions
  • Previous experience in working with teams while capable of working independently and precisely
  • Good communications skills
  • Greek (or EU / Schengen) citizen or holder of a valid Greek work permit
  • Are you interested in this challenging position within an international work environment in a successful company? Apply now! You will be working with a motivated team in an exciting technology.

    We are looking forward to receiving your application.

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