Senior Verification Engineer Athens
Dialog Semiconductor
Athens , Greece
πριν από 4 μέρες

The role

  • Execute on DMS design verification of Connectivity products including generation of test vectors
  • Owner of (part of) Verification plan, and the AMS / DMS verification of the SoC
  • Develop innovative software and hardware solutions for verification and ATE production test setups used in high volume IC manufacturing
  • Collaborate in a multi-disciplinary environment with design and test engineering.
  • On-time delivery of the SoC DMS verification with focus of first time-right design
  • Drive and own the technical conception, methodology and definition of the test / verification solution.
  • Act as technical interface between the engineering teams and rest of test & product team.
  • Work closely with engineering during the design phase to ensure solid understanding of design and product details
  • Remove impediments for the team and ensure that all pre-requisites are available and documented in the test description in time to help optimize test and product engineering efforts
  • Perform test program and hardware reviews including but not limited to test time reduction through analyzing tests requested and only implement what is must and needed
  • Drive technical innovation in the department and delivering lessons learned for test development after each project to continuously fine tune design and test interface, along with test program development and early trim implementation for the silicon
  • Ensure re-usability of existing test modules for a new program to reduce cost of development
  • Test development schedule achieved in time
  • Continuous optimization of the test vector generationContinuous optimization of minimization of the number of test vector debug iterations.
  • Budgeted development cost and test time target achieved
  • Production ramp in time and all customer shipments delivered according to schedule
  • Deliver test description in quality and detail
  • What we are looking for

  • Excellent team player with strong and assertive personality
  • Must is a proven track record in design and verification of mixed signal ICs
  • Experience in Embedded SW : Verification and test vectors make use of (small) SW (C) programs that run on M0+ or M33
  • Experience in understanding of System Verilog and Verilog AMS
  • Preferred is a good understanding of ATE test development, Basic understanding of design blocks, topologies and how they get tested in production
  • Thorough understanding of mixed signal devices and associated test / verification concepts
  • Ability to take decision and to prioritize work demonstrating strong leadership
  • Ability to work under pressure and with multi-site, multi-national teams
  • Excellent interpersonal, organizational and communication skills
  • Fluent written and verbal English is essential
  • Engineering degree in Electronics or equivalent education
  • Minimum of 5+ years’ experience in Design and verification (Radio / analog or / and digital) for mixed-signal and / or connectivity ICs
  • Previous experience preferred in writing and owning verification plan and test plan.
  • Background / understanding of the design of mixed signal circuitry is a must
  • Experience in AMS / DMS verification environments and using them (environments making use of Cadence, Simvision)
  • Experience in Embedded SW : Verification and test vectors make use of (small) SW programs (C) that run on M0+ or M33
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