Position : IC Digital Design Engineer
To support the design of next-generation SoCs in positioning and cellular applications, u-blox Athens is looking for a passionate and talented engineer, interested in digital IC design with experience in Design-for-Test.
To work in u-blox IC team you need to be creative, innovative, enthusiastic about new technologies, and striving for excellence.
The ideal candidate will start working on real project tasks in close collaboration with other teams. Through teamwork, training and dedication to personal development, u-blox goal is that every engineer quickly learns about different aspects of designing complex SoCs, starts contributing to various project tasks, and finally develops into an expert in the field.
Key responsibilities of a digital IC engineer will be to contribute / drive the requirements and specification analysis phase, the micro-architectural definition, the digital design (RTL), definition and integration of DfT architecture, as well as, performing scan-insertion, and pattern generation and debugging.
The engineer should work with the rest of the design, verification and DfT teams to meet the targeted specifications.
Involved in the entire design process of key IPs, including RTL design, top-level integration, verification, synthesis, Lint / CDC violations checking, etc
Contribute to the requirements / specification analysis and micro-architectural definition
Perform power analysis and propose design optimizations (area, timing, power)
Writing-up DfT specifications
Design / Integrate DfT structures as required
Responsible for SCAN insertion and pattern generation
Writing DfT related SDC constraints
Support failure analysis
Support test-program development
Perform test planning, verification coverage analysis and performance evaluation
Full IP verification using testbench based testing and coverage-driven verification techniques
Contribute to the IP top-level integration and FPGA prototyping for early IP testing at top-level
IP API development for testing purposes (SoC-level simulation, FPGA, silicon testing)
Utilize and evolve u-blox digital IC and FPGA flows
Plan, track, and report for the key IP activities
Responsible for technical documentation and reports (English language)
PhD / MS or BS in Electrical, Electronic, Computing Engineering or equivalent experience
3+ years of industrial experience in digital IC, ideally with focus on Design-for-Test
Excellent in logic design including algorithmic-based optimization, from power, performance and area perspective
Experience in DfT : knowledge about industrial standards and practices in DfT, including ATPG, JTAG, MBIST, LBIST and trade-offs between test quality and test time
Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, LBIST and JTAG related issues
Experience with STA constraints development and analysis for DfT modes and SDF simulations
Experience with top-level synthesis
Experience in cross interaction with DfT and physical design team
Familiarization with lab equipment and procedures for silicon testing
Experience in design of multiple clock and power domain architectures
Experience in efficiently porting top-level RTL in FPGA and achieving timing-closure
Familiar with Unix / Linux environment, shell programming, revision control systems and scripting (C-shell, Tcl, Perl, Python)
Strive for innovation and adoption of leading edge solutions
Previous experience in working with teams while capable of working independently and precisely
Good communications skills
EU citizen or holder of a valid Greek work permit
Learn more about u-blox and its mission by watching !
We see diversity as a strength and promote a culture of inclusion among our employees. Our varied backgrounds, ideas and experiences are critical to our success.
We strive to become a strong learning organisation and are committed to provide our employees with equal opportunities regardless of differences such as gender, race, ethnicity, generations, belief.